In numerous applications of semiconductor electronics it is advantageous for a semiconductor device in circuits integrated therein to include in addition to one or more MOS transistors also one or more bipolar transistors. Any such device will be referred to in this application as a BiMOS semiconductor device. When the MOS transistors comprise complementary transistors, i.e., n-channel transistors and p-channel transistors, it is referred to a BiCMOS semiconductor device.
Typical fields of application of bipolar transistors in BiCMOS semiconductor devices are, for example, low-noise amplifiers and constant current sources. For integration into a BiCMOS process there are known many structures of bipolar transistors. For instance, to this end it may be referred to the volume S. Wolf: “Silicon Processing For the VLSI Era”, Vol. 2: Process Integration; Lattice Press, Sunset Beach, Calif., 1990.
The integration of bipolar transistors into a CMOS process, however, requires additional efforts compared to a pure CMOS process flow. Bipolar transistors are fabricated in the context of process modules that add additional masking steps to the CMOS process.
The technical object underlying the present invention is to provide a BiMOS semiconductor device that comprises in its integrated circuit a bipolar transistor in addition to a MOS transistor, wherein the bipolar transistor is configured such that it can be fabricated with particularly low effort.